The system and method disclosed herein relate to integrated circuit performance modeling and, more particularly, to determining merged resistance values for same-type terminals of multiple electrically connected semiconductor devices (e.g., multiple electrically connected field effect transistors (FETs) or multiple electrically connected bipolar junction transistors (BJTs)) in a complex semiconductor structure so that such merged resistance values can subsequently be used in integrated circuit performance modeling.
Traditional techniques for generating a performance model for an integrated circuit (i.e., a model of integrated circuit behavioral characteristics, current-voltage (I-V) characteristics, etc.) require extraction of a full netlist from the design layout of the integrated circuit. This full netlist will include all active devices and many parasitic resistive elements. Examples of parasitic resistive elements include diffusion resistance, contact resistance, local interconnect resistance, via resistance, metal wire resistance, etc. The values of these parasitic resistance elements are temperature dependent but are voltage independent generally (or, say, in their intended operational voltage range). The behavior of active devices is both temperature-dependent and voltage-dependent. Simulations of the full netlist are performed over the full range of operating temperatures, over the full range of operating power supply voltages and, optionally, taking into consideration other factors that may impact performance (e.g., self-heating and stress). Additionally, repeated simulations may be required for model calibration and/or to accommodate design modifications or options. The integrated circuit performance model can be generated based on the results of the simulations.
Unfortunately, as more and more complex semiconductor structures having multiple electrically connected multi-terminal semiconductor devices are incorporated into integrated circuits the use of such traditional techniques to model integrated circuit performance has become impracticable, given the amount of time required to complete the simulations and generate the integrated circuit performance model.